Do CPUs that support 5-Level Papging implement a 57-bit long address bus?

All we need is an easy explanation of the problem, so here it is.

Despite having a data bus size of 64 bit, the address bus size of modern AMD64-compatible CPUs is/was 48 bit for some time which allows using 48-bit long virtual memory addresses with a maximum of addressable virtual memory of 2^48 => 256 TB.

Intel says [1] that since the Ice Lake CPU architecture, their CPUs support 5-Level Paging with 57-bit long virtual memory addresses. Linux supports this since Kernel 4.14 [2].

Does this mean that CPUs that support 5-Level Paging with 57-bit long virtual memory addresses implement a 57-bit long address bus?

The background of my question is that around 10-15 years ago, it was not a problem to learn about the address bus and data bus size of modern CPUs, but since approximately ten years, it is not simple to find information about the address bus size.

[1] https://software.intel.com/content/www/us/en/develop/download/5-level-paging-and-5-level-ept-white-paper.html

[2] https://www.kernel.org/doc/html/latest/x86/x86_64/5level-paging.html

How to solve :

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Method 1

No, they implement (at most) a 52-bit address bus. 4- and 5-level paging is described in section 4.5 of the Intel® 64 and IA-32 Architectures Software Developer Manuals, Volume 3A:

5-level paging translates 57-bit linear addresses to 52-bit physical addresses.

As far as I’m aware, current Intel CPUs support at most 6TiB of RAM per socket (see for example the 8362), which is less than 243; so I suspect that, even though the address bus covers more than physical memory, there are fewer than 52 address pads on the CPU (in socket 4189).

Note: Use and implement method 1 because this method fully tested our system.
Thank you 🙂

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